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Salvatore Frandina

Salvatore Frandina was born in Siena on 14th march 1985. At the moment he is attending a PhD school in Information Engineering at University of Siena with a research line in Artificial Intelligence (adaptive systems for information processing).
In 2010 he graduated cum laude in Telecommunications Engineering (Master Degree) at the University of Siena, Italy, discussing a Thesis on "Videoconference for the Asterisk VoIP PBX: study and implementation". In 2007 he graduated cum laude in Telecommunications Engineering (Bachelor Degree) at the University of Siena, Italy, discussing a Thesis on "Realization on FPGA of a control system to increasing the entropy of random bits generator".

Interest

  • Machine Learning:
    • Semantic based regularization;
    • Pattern recognition;
    • Integration of symbolic and sub-symbolic models for information processing.
  • Videoconference for Asterisk:
    • VoIP protocols (SIP, IAX2, H.323);
    • AppConference, MCU media mixer, CONFIANCE, VMukti.
  • Segmentation of retinal vasculature:
    • Wavelets (Gabor and Morlet);
    • Supervised classification (GMM, k-NN, LMSE, SVM);
    • Public image database (DRIVE, STARE).
  • Random bits generator:
    • Complexity Theory and Information Theory;
    • Random and Pseudo-Random Number Generators;
    • Cryptographic algorithms;
    • FPGA and integrated circuits.

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  • Master Degree Thesis / Tesi di Laurea Specialistica
    (In Italian only)
    "Videoconferenza per il centralino VoIP Asterisk: studio e implementazione".
    Relatore: Prof. A. Andreadis - Correlatore: Ing. S. Bonelli - A.A. 2008/2009. (Abstract)

 

  • Vessel Segmentation Project / Progetto di segmentazione dei capillari
    (In Italian only)
    "Studio delle tecniche di segmentazione dei capillari su fondo oculare".
    Relatore: Prof. A. Mecocci - A.A. 2008/2009. (Abstract)

 

  • Bachelor Degree Thesis / Tesi di Laurea Triennale
    (In Italian only)
    "Realizzazione su FPGA di un sistema di controllo per l'incremento dell'entropia di un generatore di bit casuali".
    Relatore: Prof. V. Vignoli - Correlatore: Ing. T. Addabbo - A.A. 2006/2007. (Abstract)